Laser annealing using a scanned annealing laser beam offers an ultra-low thermal budget, a high dopant activation and super-abrupt junctions that are ideal for advanced semiconductor device fabrication. Consequently, most logic devices with minimum feature sizes below 45 nm, and many memory devices below 32 nm, now use some form of laser processing for one of several manufacturing steps, including source-drain activation, metal-silicon alloy formation, defect annealing, and the like.
In all of these semiconductor fabrication applications, the width of the scanned annealing laser beam is significantly smaller than the width of the semiconductor wafer that supports the semiconductor device structures as they are being fabricated. As a result, it becomes necessary to scan and “stitch” the beam over the wafer when annealing the semiconductor device structures.
Unfortunately, the semiconductor device structures under fabrication that lie in the stitch overlap region may not be annealed in exactly the same way as those devices in the middle of the beam. This is because the devices in the overlap region see the tails of the annealing beam and may not be annealed to the same temperature as the region in the center of the annealing beam.
In addition, the semiconductor device structures in the overlap regions see the tail beam twice from adjacent scans of the annealing beam. As a result, there can be degradation in the uniformity of the annealing of the semiconductor device structures across the wafer.